Testability driven Synthesis of non-scan data-paths

We present in this paper, a behavioral synthesis method aimed at generating testable designs. A non-- scan testing strategy is targeted. Given performance and area constraints, the primary goal of this system is to seek among equivalent design alternatives the one that exhibits the least testability problems. Its second objective is the easiness for sequential automatic test pattern generator to generate test patterns. The backbone of this methodology is a testability analysis methods, that works at different abstraction levels of design description (from purely behavioral to purely structural). Its able to predict the testability of the future structure's modules. Synthesis tasks, such as register allocation and interconnect network generation, aimed at improving testability are detailed. keywords High Level Synthesis, Synthesis for Testability, Non--scan designs, Introduction Due to the increasing complexity of VLSI systems, numerous techniques are developed in order to reduce te..

A new TPG structure for Datapath cores

The BIST approach discussed in this paper is based on the modification of pre-existing registers to perform test pattern generation (TPG). We present a new TPG structure particularly well-suited for datapath like cores. Generated test sequences are short and lead to high fault coverage for the most common modules in a datapath. We compare the proposed TPG with related structures. 1. Introduction BIST advantages are well known, it allows production testing as well as maintenance testing, it doesn't need expensive Automatic Test Equipment and allows at speed testing. Per contra, BIST involves additional cost in terms of extra hardware for test pattern generation (TPG) and signature analysis (SA). Consequently, a BIST implementation is evaluated in terms of area overhead, achievable faultcoverage and test length resulting from the generated test sequence. These characteristics depend on the targeted test approach. In pseudo-random testing for example, test sequences can be easily genera..

Alleviating DFT cost using testability driven HLS

This paper presents a method to carry out the register allocation phase of High Level Synthesis with testability considerations. Testability problems are identified and eliminated during this step turning testability/area tradeoff to account. It allows to decrease the cost related to the application of low-level DFT techniques. Keywords : High level test synthesis, resource sharing, register allocation, DFT 1 Introduction High Level Synthesis (HLS) consists to generate a register transfer level (RTL) structure from a user provided behavior. In general, it is possible to obtain various RTL structures that implement a given behavior. These structures differ in some aspects, like area, speed, power or testability. HLS algorithms are guided by user provided constraints in order to favor one or several particular features. With respect to testability issues, many commercial synthesis tools operate at lower level, namely at RT or gate level. They introduce dedicated test structures that ..

ÉTUDE PHOTOÉLECTRIQUE DES PERTES D'ÉNERGIE DES ÉLECTRONS DANS LES STRUCTURES ALUMINIUM-ALUMINE-ALUMINIUM

L'effet photoélectrique interne dans les structures aluminium-alumine-aluminium est interprété en rejetant l'hypothèse d'interactions très énergétiques dans l'alumine. Ceci permet une détermination originale du travail de sortie aluminium-alumine qui ne nécessite plus de mesure d'énergie incidente. Ces expériences permettent d'atteindre la valeur de la longueur d'atténuation en énergie des électrons dans l'aluminium et le rapport des probabilités de transfert dans l'alumine, dans le sens et en sens contraire de la force électrique. On peut en outre évaluer la perte d'énergie moyenne de ces électrons « chauds » qui est de l'ordre de 0,01 eV dans une couche d'alumine de 35 Å d'épaisseur.Experiments on the interna1 photoelectric effect in thin films aluminium-alumina-aluminium sandwiches are interpreted on the assumption of low energy interactions in alumina. This gives an original method for the determination of the aluminium-alumina work function, which is in fact a Fowler diagram, but does not need incident energy measurements. From these experiments it is possible to deduce the value of the electron energy attenuation length in aluminium and the ratio of the transfer probabilities dong and against the electric strength. The mean energy loss of hot electrons in alumina can be evaluated, it is found to be of the order of 0.01 eV in a 35 Å thick alumina film